The invention is directed to an improved approach for designing, testing, and manufacturing integrated circuits.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. In particular, an integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
Based upon this geometric information, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
Other processes may also occur during the process of manufacturing an integrated circuit. For example, etching, electroplated copper deposition (ECD), and chemical mechanical polishing (CMP) may be used to form interconnects for the IC. The lithographic patterns define the dimensions of the circuitry that is transferred to a silicon wafer, with the patterns subsequently used with the etch process to physically etch the features into the wafer surface or other thin films deposited on the wafer surface. Etch equipment includes mechanisms to selectively remove materials (e.g. oxide) from a wafer surface or thin films on the wafer surface patterned with lithography equipment. ECD is a process step in a copper damascene flow that is used to deposit copper material within the interconnect structures.
However, significant variations may arise during the process of manufacturing the IC, such as variations in feature density, widths, and heights caused by lithography, etch, CMP, and/or deposition processes. For example, variations based upon CMP and deposition process are often caused by dielectric loss, dishing, erosion, or other metal losses.
One way to reduce the variations in fabricated chips is to use a pattern-dependent model to predict variations of feature dimensions of an integrated circuit. Pattern-dependent models can also be used to predict topological variations of an integrated circuit. Further details regarding one approach for implementing and using pattern-dependent models is disclosed in US Patent Publication 2003/0229412, filed on Dec. 11, 2003, entitled “Electronic design for integrated circuits based on process related variations,” which is hereby incorporated by reference in its entirety.
At semiconductor manufacturing process node 65 nm and beyond, it becomes more and more useful for the designer to have access to accurate modeling of systematic variations, e.g., variations caused by manufacturing issues such as Chemical Mechanical Polishing (CMP), etch and lithography. These models are very useful at the design stage for achieving higher chip performance, yield, and time-to-volume.
Recently, modeling has been introduced to predict full chip wire thickness and chip surface topography variation (e.g. caused by the CMP process). It has been demonstrated that by using design-specific thickness profile predicted by a calibrated CMP model, resistance and capacitance (R and C) extraction values are more accurate compared to traditional approaches (e.g. using a fixed nominal or a rule-based thickness lookup table).
While model-based approaches are better than rule-based approaches in accounting for manufacturing variations, current uses of full-chip modeling are limited to the sign-off stage, when the design (including dummy metal fill) is completed. However, RC extraction is often used earlier in the design implementation flow on IP or macro blocks, where early timing closure is a key to a fast chip design. During the early-stage design phase, each IP or macro block is implemented independently, and the lack of full-chip information and the lack of sufficient time to repeatedly perform long simulations prevents full-chip models (e.g. CMP and etch) from being utilized to more accurately extract resistance and capacitance. Also, block designers typically think and operate in terms of their design, rather than from the perspective of the full-chip design.